In the integrated circuit (IC) industry, the performance of metal oxide semiconductor (MOS) field effect transistors (FETs) are controlled by two primary device characteristics. The performance of a MOSFET device can be enhanced by reducing the length of a gate electrode of the MOSFET device, and/or reducing the gate dielectric thickness of the MOSFET device. The integrated circuit industry has progressed to a point where thermal gate oxide thickness is becoming less than roughly 60 angstroms. As gate dielectrics progress to a thickness less than 60 angstroms, a theoretical and practical limit to thermal gate oxidation is now being approached. Therefore, the integrated circuit industry is attempting to develop materials which can replace thermal oxides as gate dielectric materials in order to continue to progress the performance of MOS transistors to new levels.
For this purpose, silicon nitride (Si.sub.x N.sub.y) materials have been proposed as a potential gate dielectrics to replace thermal oxide gate dielectrics. Since the dielectric constant of silicon nitride material is roughly twice that of thermal oxide (8.0 versus 4.0), a thicker silicon nitride layer can be physically deposited while achieving a similar equivalent oxide thickness (EOT) of a thinner thermal oxide gate dielectric. For the purpose of illustration, a silicon nitride gate dielectric deposited to a thickness of roughly 80 angstroms is roughly equivalent to a thermal oxide gate dielectric deposited to a thickness of 40 angstroms in terms of MOSFET performance whereby thinner EOT are more advantageous to MOSFET performance. This physical increase in gate dielectric thickness while maintaining similar levels of EOT/performance is advantageous since the physically thicker nitride layer can reduce gate to channel leakage current while MOSFET performance is not adversely impacted.
A first prior art silicon nitride solution for gate dielectric formation utilizes a low pressure chemical vapor deposited (LPCVD) silicon nitride material. As an alternative to this technique, rapid thermal chemical vapor deposition (RTCVD) silicon nitride films have also been proposed for use to replace thermal gate oxides. The use of these LPCVD and RTCVD silicon nitride layers as gate dielectrics is not advantageous. First, these silicon nitride layers suffer from high hydrogen concentrations which result in significant electron trapping which adversely effects MOSFET threshold voltages (V.sub.t). It has been experimentally observed that these LPCVD silicon nitride and RTCVD silicon nitride layers experience unstable capacitance-voltage (C-V) performance and unstable current-voltage (I-V) performance. Furthermore, these silicon nitride films are readily oxidized in an oxygen-containing ambient wherein this oxidation will occur in a highly uncontrollable fashion. Since this oxygen concentration controls the relative permittivity (e.sub.r) of the material and thereby controls the performance of the MOS device, this uncontrolled oxidation of the silicon nitride layer is disadvantageous and causes radically different MOSFET performance wafer-to-wafer and lot-to-lot.
Another solution proposed in the art is to utilize LPCVD or RTCVD silicon nitride layers which are exposed to a rapid thermal processing (RTP) post-anneal process utilizing N.sub.2 O, While this post-anneal solution results in MOSFETs with a more stable capacitance-voltage (C-V) performance and a more stable current-voltage (I-V) performance, the oxidation of these layers still remains as a disadvantage. The uncontrolled oxidation of exposed post-annealed nitride layers results in a significant lowering of the material's dielectric constant thereby reducing transistor performance by increasing the EOT value. Dielectric constants on the order of e.sub.r =4.7 have been measured for these nitride materials whereby this dielectric constant is not a great improvement over the existing thermal oxide dielectric constant of roughly e.sub.r =4.0.
Another solution in the integrated circuit (IC) industry has been to form a silicon nitride layer by direct nitridation of the exposed Si of the channel region of a MOSFET using an ammonia (NH.sub.3) ambient. This method also suffers from ambient oxidation of the nitride after film formation, whereby the dielectric constant (e.sub.r) of the completed gate dielectric film can be adversely affected as previously discussed. Furthermore, the thickness of material which can be nitrided using this nitridation process is inherently self-limiting whereby adequately thick gate dielectric materials cannot be formed using this process. While plasma processing may allow for the formation of thicker gate oxides using this process, the ambient oxidation of this film is still a limiting factor in the use of this technology.
Another proposed solution to this gate dielectric problem has been membrane dielectric technology. While this technology forms stable MOS transistors have stable CV performance and IV performance, the significant oxygen concentration of these membrane dielectrics adversely affects the dielectric constant whereby MOSFET performance is also adversely impacted.
Jet vapor deposition (JVD) of silicon nitride materials has been proposed for use as gate dielectrics for MOSFETs. While these materials form stable MOSFETs having stable C-V performance and stable I-V performance, the oxygen contamination of these JVD materials is high. Experimentation has shown significant ambient oxidation of the silicon nitride surface after deposition whereby dielectric constants (e.sub.r) for these materials are typically less than the dielectric constant of unoxidized silicon nitride materials.
Therefore, the need exists for a new high-K material which does not suffer from reduced C-V and I-V performance and is not adversely oxidized by oxygen-containing ambients. This new gate dielectric should have some oxygen that is selectively formed near the interface to silicon materials to provide the necessary oxygen to create a quality gate dielectric film. In addition, this new gate dielectric must avoid the uncontrolled oxidation found in the prior art when the prior art is exposed to an oxygen ambient. Substantial gate dielectric oxidation needs to be avoided so that the resulting permittivity of the gate dielectric material is not adversely reduced whereby MOSFET performance (i.e. gate leakage current) is affected. In addition, bulk oxygen profiles and concentrations of this new gate dielectric should be low enough and stable enough over time to avoid degradation of the dielectric constant (e.sub.r). This gate dielectric will enhance MOS transistor performance over conventional thermal gate dielectric layers and other known nitride gate dielectric solutions.
Silicon dioxide is typically used for gate oxides due to the fact that it can be relatively easily formed and has well known properties and a high quality interface with silicon. However, as devices continue to be scaled to smaller dimensions, the thickness of a silicon dioxide layer becomes too small to make a robust gate dielectric film. Therefore nitride and nitride-like layers are being examined because they have higher dielectric constants compared to silicon dioxide. However, problems can occur when forming the nitride compounds. More specifically, conventional LPCVD depositions of silicon nitride form a layer that has a relatively high amount of electron traps due to a low nitrogen to silicon atomic ratio and a high hydrogen content. Also, the atomic ratio of nitrogen to silicon in the deposited film is essentially constant over a wide range of ammonia to dichlorosilane gas flow ratios. Conventional LPCVD are lengthy processes because of a low deposition rate coupled with lengthy heat up and cool down times. Additionally, conventional LPCVD processing may have adverse effects on the electrical characteristics of the device being formed.
One attempt to address the problem would be to replace a dichlorosilane with a fully chlorinated silane compound. The more chlorinated the silane compound is, generally, the higher the temperature for the deposition. High temperature deposition should be avoided as these can move critical implants that have already been formed within the device including threshold adjusting type implants and punch-through implants.
Yet another way of trying to address the problem is to use a nitrogen-rich silicon nitride film that is formed by either a plasma-enhanced deposition or with implantation. The plasma processing typically uses silane as the source gas and will incorporate a large amount of hydrogen in the bulk. The plasma also causes plasma damage to devices during the film deposition. In yet another alternative embodiment, a conventional silicon nitride layer can be deposited followed by an implantation of nitrogen. However, this is not a good alternative as the implant will cause damage to the film. Further, it will be difficult to control the depth of the nitrogen particularly as the silicon nitride thickness becomes thinner. The nitrogen needs to be spread uniformly throughout the thickness and in almost all instances there will be at least portions of the film near its two outermost surfaces that will be deficient in nitrogen concentration. Although an anneal step can be performed after the implantation or plasma deposition, it is believed that the anneal step will not completely repair the damage that occurs.
The problems related to hydrogen within the silicon nitride film generally have to do with traps. Hydrogen related traps in the bulk increase the leakage current of the film. Traps are generally portions of an interface or layer that has dangling bonds. Traps generally are not desired and should be avoided if possible.